A Place to learn VHDL & Verilog HDL comparitively ...
Welcome
This website is dedicated to VTU students. ” Fundamentals of HDL” one of the fourth sem B.E subject is discussed in brief. We take care to explain even the most basic concepts in this subject. We have used simple language, flow charts, pop up explanations to your convenience. Hope you have better understanding of the subject after being with us.
According to the VTU syllabi this subject comprises of two parts. They are VHDL, Verilog HDL. These two subjects are dealt side by side as our syllabi progresses.
For easier understanding of VHDL & VERILOG, minimum knowledge of middle level language like C is required.To facilitate you basics of C are included whenever necessary. For basics refer third sem subject logic design.
Queries and discussions at: vigyan.forumotion.net
