chap1 styles of description of hdl code

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Chapter 1. styles of description

Styles of descriptions:
There are different styles of writing the descriptions both in VHDL and Verilog. These styles are broadly classified into 7 types as shown below. These styles are common to VHDL and Verilog HDL.

1. Behavioral description:
A behavioral description is based on the manner in which outputs behave with the inputs. In VHDL the architecture includes the keyword “process”. In Verilog “always” or “initial” is used.

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2.Structural description:
In this description the entire system is modeled as components or gates. The description is identified by the presence of the key word “component” in architecture in VHDL. In Verilog it is identified by gates construct eg and, or.

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3.Switch description:
The system is described into switches or transistors. Verilog uses keywords to describe the system. VHDL does not have built in switch level primitives but we can attach packages which contain them.

An Example of Switch-Level Description. a) VHDL. b) Verilog
a) VHDL Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Inverter is
    Port (y : out std_logic; a: in std_logic );
end Inverter;

architecture Invert_switch of Inverter is
component nmos
--nmos is one of the key words for switch-level.
port (O1: out std_logic; I1, I2 : in std_logic);
end component;

component pmos
--pmos is one of the key words for switch-level.

port (O1: out std_logic ;I1, I2 : in std_logic);
end component;

for all: pmos use entity work. mos (pmos_behavioral);
for all: nmos use entity work. mos (nmos_behavioral);
--The above two statements are referring to a package mos
--See details in Chapter 5
constant vdd: std_logic := '1';
constant gnd : std_logic:= '0';
begin
p1 : pmos port map (y, vdd, a);
n1:  nmos port map (y, gnd, a);
end Invert_switch;

b) Verilog Description

module invert(y,a);
input a;
output y;
supply1 vdd; 
supply0 gnd;
pmos p1(y, vdd, a);
nmos n1(y, gnd, a);
--The above two statement are using the two primitives pmos and nmos
endmodule

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4.Data flow description:
Data flow description shows how the signals flow from the inputs to the output. The data flow statements are concurrent. The description usually has Boolean expression of its outputs.

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5.Mixed type description:
Mixed type usually has more than one style of the descriptions in them. They are used in large sized programs.
6.Mixed language description:
Mixed language description is a new tool in which the user can write module in Verilog and entity from VHDL using “import a construct”.

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