Vhdl reserved words

The following identifiers are reserved words^** in the language (also called keywords), and therefore, cannot be used as identifiers (or variables) in a VHDL description.

Abs    access    after    alias    all    and   architecture   array    assert     attribute

begin    block     body     buffer bus

case     component     configuration     constant

disconnect   downto

else    elsif     end     entity   exit

file    for     function

generate   generic guarded

if    in     inout     is

label    library     linkage    loop

map     mod

nand    new     next     nor   not     null

of    on     open     or   others     out

package   port       procedure     process

range    record     register    rem   report     return

select    severity    signal     subtype

then    to     transport    type

units    until     use

variable

wait   when       while       with

xor