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Datatypes in VHDL & Verilog HDL
HDL is a language used to describe the hardware of a system. The data used in the hardware system is of several types to match the need for describing the hardware.
The breif description of the data types used in VHDL and Verilog HDL is shown below.
VHDL Data types:
VHDL is a type oriented language. Many operations cannot be executed without choosing the right type of data types for the operands. There are 5 major data types. They are described below.
1.Scalar type:
The values of the scalar object types are numeric. It is sub divided into 8 types.
Bit type: the only value used is 0 or 1.
Boolean type: the only value used is true(1) or false(0).
Integer type: all integer values are used. “range” is used to define a shorter range of integer. “natural” is used when all values are positive.
Real type: this type accepts fractions.
Character type: this type includes characters that can be used to print a message. This is done by “report” command.
Physical type: this type has values that can be measured in units. Ex time.
User defined: the user can define a type using “type” followed by identifier.
Severity type: this type can take one of the four values note, warning, error, failure.
2.Composite type:
The composite data type is a collection of values. There are 3 composite data types.
Bit_vector: this data type represents a array of bits. It is denoted as shown in example.
I1: in bit_vector(3 down to 0); it has 4 bits.
Array type: this type is defined by using the pre defined word “array”. Arrays can be multi dimensional (similar to arrays in C).
Record types: this data type can be composed of same or different data types (similar to structures in C).
3.Access type: values belonging to access are pointers to objects of other types(similar to pointers in C).
4.File types: objects of this type can be read and written using built in functions(similar to files in C).
5.Other types: these are functions provided by external libraries. Respective packages containing these types should be attached. It has 4 types under it. They are
Std_Logic type: this logic has 9 values including 1 and 0. Package “std_Logic_1164.all” should be attached.
Std_logic_vector type: this type represents a array. Each element is of type std_logic. Package “std_Logic_1164.all” should be attached.
Signed: signed is a numeric type declared in external library “numeric_std”. It represents signed integers in the form of array.
Unsigned: unsigned is a numeric type declared in external library “numeric_std”. It represents unsigned integers in the form of array.
Verilog HDL data types:
Verilog doesn’t have extensive data types like VHDL. It has 7 different data types.
1.Nets: nets are declared by the predefined word “wire”. Nets have that values that are continuously changing throughout the program.
2.Registers: registers are declared by the predefined word “reg”. registers store values until they are updated.
3.Vectors: vectors are multiple bits declared by brackets []. A register or net can be declared as a vector.
4.Integer: integers are defined by predefined word “integer”.
5.Parameters: they represent global constant. Represented by pre defined word “parameter”.
6.Arrays: registers and integers can be written in arrays. Multi dimensional arrays are not supported in Verilog.
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