VHDL start page

VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The language was standardised by IEEE in December 1987. Verilog was standardised by IEEE in the year december 1995.

Vhdl has a rigid structure which makes learning difficult at beginner level but advanced users make good use of the rigid structures in VHDL to make their designing easier. VHDL is mostly used to describe a system at a higher level.